The Manifesto

Vecto + Nexus.

Two words. One bridge. This is the technical meaning behind the name — and the philosophy every project we build has to answer to.

01 · Vecto

The software logic.

Short for Vector. In hardware, vector processing handles parallel math instructions — the crucial mechanism behind modern CPUs and NPUs, letting silicon execute the same operation across many data points at once instead of one at a time.

In software, vectors dictate data memory paths and computational direction — the route an instruction takes from register to ALU to memory and back. Understanding that route is the difference between code that merely runs and code that runs fast.

Vecto is our commitment to that low-level fluency: we don't treat the hardware as a black box that software happens to sit on top of.

vector_op.asm
; scalar: one lane, one cycle each
ADD  R1, R2, R3
ADD  R4, R5, R6
ADD  R7, R8, R9

; vector: N lanes, one instruction
VADD.f32  V0, V1, V2   ; 8 lanes wide
→ parallel across the NPU's SIMD units

; direction is the point:
// data path chosen = performance won or lost

Nexus node — six vectors radiating from a central core
02 · Nexus

The core connection.

Nexus represents the central meeting point where multiple independent systems join together — the node every one of our six radiating vectors returns to in the mark above.

A compiler team, an RTL team, a firmware team, and an ML team can each optimize their own layer in isolation and still ship something that doesn't work end to end. Nexus is the discipline of designing the seams between those layers on purpose, instead of leaving them to chance at integration time.

The Narrative

The name literally translates to “The Central Hub for Parallel Compute.”

It positions VectoNexus as the core bridge where software logic seamlessly matches physical hardware channels — not a hardware company that ships software as an afterthought, and not a software company that treats silicon as someone else's problem.

Why We Build in the Open

Openness isn't a license file. It's the architecture.

Closed silicon and closed toolchains ask you to trust a black box. We think engineers deserve to see the datapath.

Auditability

Every control signal, every instruction path, every line of RTL is inspectable. Trust comes from being able to check, not from a vendor's word.

No Vendor Lock-in

Permissive licensing by default. Fork it, retarget it, ship it commercially — the ecosystem grows when nobody has to ask permission.

Privacy by Architecture

On-device AI means inference happens close to silicon — data doesn't need to leave the device to be useful.

Who We Are

A research-oriented team, not a product shop.

VectoNexus started as engineers who wanted to see the whole datapath — from transistor to tensor. We publish our work as we build it, share what we learn even when it's incomplete, and treat every repository as an invitation to argue with our design decisions in the open.

See the Work