What we're building.
Active builds, research in progress, and the roadmap ahead — every repository open from the first commit.
ARM Single-Cycle Datapath Visualizer
Our flagship open hardware build: a from-scratch, cycle-accurate visualization of the classic single-cycle ARM datapath — the same architecture taught in every computer organization course, rebuilt as an interactive tool instead of a static textbook diagram.
Cycle-by-cycle tracing
Watch every instruction move through Fetch → Decode → Execute → Memory → Writeback, with control signals lighting up in real time.
Interactive datapath
The ALU, register file, control unit, and memory paths are rendered as a live diagram you can trace instruction-by-instruction.
Built for learning
Designed for classrooms and self-learners who want to see how a CPU actually moves data — not just read about it.
What's next on the bridge.
RISC-V Pipelined Core
Extending the single-cycle visualizer's philosophy to a pipelined RISC-V core — hazards, forwarding, and branch prediction made visible.
On-Device NPU Compiler
A lightweight compiler backend targeting edge NPUs — mapping vectorized ML ops directly onto parallel silicon.
Open Reference PCB Designs
Schematic-to-silicon reference boards for hobbyists and researchers to prototype open architectures on real hardware.
Have an idea that fits the mission? We build in the open — pitch it as an issue.
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